Electronic Design

FPGA Tool Suite Adds Native Static Timing Analysis

With so many ASIC designers moving over to FPGAs for implementation, FPGA tool flows are looking more and more like ASIC flows. Case in point: Actel's Libero IDE 6.2 adds native static timing analysis ...
Electronic Design

Timing Checks Go Full Chip

Nanometer design will require new thinking in timing closure. Historically, design teams relied on static timing analysis, which depends on the abstracted behavior of individual gates to perform ...
EDN

Taking the guesswork out of timing in real-time software systems

Guaranteeing correct operation of real-time software running on an embedded processor is a significant challenge. Data dependent execution flows, where execution times of many functions are dependent ...
Semiconductor Engineering

Closing The Post-Silicon Timing Analysis Gap

Accurate static timing analysis is one of the most important steps in the development of advanced node semiconductor devices. Performance numbers are included in chip and system specifications from ...