The move to multi-die packaging is driving chipmakers to develop more cost-effective ways to ensure only known-good die are integrated into packages, because the price of failure is significantly ...
GRENOBLE, France--(BUSINESS WIRE)--Hprobe, a provider of turnkey semiconductor Automatic Test Equipment (ATE) for magnetic devices, today announced a breakthrough magnetic test head revolutionizing ...
The high costs of building, resourcing and operating a foundry fabricating integrated circuits are well known. Fabless companies avoid this capital cost and focus on design and innovation in their ...
Test-flow partitioning between wafer sort and final package test can have a dramatic impact on the cost of test. In some cases, the migration of package tests can be done over time, but the test ...
SANTA CLARA, Calif. – Looking to reduce the soaring costs of IC test, Intel Corp. hopes to leverage its “causal learning algorithm” technology for wafer sorting applications in the fab. Intel is ...
The back-end semiconductor manufacturing process refers to the IC packaging and testing that people often hear about. Specifically, the process known as chip probing (CP) is conducted to test the ...
The emergence of 3-D ICs presents test challenges that extend from design-for-test tools from design-automation companies to device handlers from equipment firms including Advantest and Multitest. A ...
May 19, 2011, 4:17 PM EDT / Source: GlobeNewswire FREMONT, Calif., May 19, 2011 (GLOBE NEWSWIRE) -- Aehr Test Systems (Nasdaq:AEHR), a worldwide supplier of semiconductor test and burn-in equipment, ...
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