SANTA CRUZ, Calif. — In theory, static timing analysis and formal verification should render gate-level simulation unnecessary. But in reality, it's unavoidable, according to a number of engineers who ...

Complexity mounts, driven by multiple dies, larger and more complex systems, and the incessant demand for performance improvements everywhere.

In recent years, formal verification has become the verification methodology of choice for many designers and verification engineers. It's now in the mainstream marketplace, as it's easy to use, ...

Reducing simulation debugging time, the compiled-code Verilogger Extreme Verilog 2001 simulator provides fast simulation of RTL and gate-level simulations using SDF (Synopsys Delay Format) timing ...

The Unified Power Format (UPF) is used to specify the power intent of a design. Once written, the UPF file is applied at every stage of the design cycle — starting with the RTL, then the gate-level, ...

Figure 1. (click to enlarge) Part-level flow simulation. The diversity and complexity of medical devices are likely to increase with time, as will the associated design risks and manufacturing ...

In Part 1, we reviewed the process of designing a modern hardware emulation platform. Here, we’ll look at the skills and training that are necessary to become a simulation expert and an emulation ...